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copyright ? cirrus logic, inc. 2010 (all rights reserved) http://www.cirrus.com advance product information this document contains information for a new product. cirrus logic reserves the right to modify this product without notice. gate drivers class-h controller advanced ? modulator gate drivers internal oscillator gain gain audio in + audio in - shutdown speaker out + speaker out - gnd vbatt 2.5v - 5v ldo filter short circuit/thermal protection mode low drop-out voltage regulator 2.9 w mono class-d audio amp lifier with low idle current cs35l01 & cs35l03 features ? filterless hybrid class-d architecture ? <1 ma quiescent current ? 1 x 2.9 w into 4 (10% thd+n) ? 1 x 2.3 w into 4 (1% thd+n) ? 1 x 1.7 w into 8 (10% thd+n) ? 1 x 1.4 w into 8 (1% thd+n) ? advanced ? closed-loop modulation ? 98 db signal-to-noise ratio (a-weighted) ? 0.02% thd+n @ 1 w (sd & hd mode) ? integrated protection and automatic recovery for output short-circuit and thermal overload ? pin-compatible 9-ball w lcsp family for easy upgrade path ? cs35l01: +6 db default gain ? cs35l03: +12 db default gain ? pop and click suppression common applications ? mobile phones ? laptops/netbooks ? portable navigation devices ? active speakers ? portable gaming general description the cs35l01 and the cs35l03 are 2.9w high efficien- cy hybrid class-d audio amplif iers with low idle current consumption. the cs35l01/03 features an advanced closed-loop ar- chitecture to provide 0.02% thd+n at 1 w and -75 db psrr at 217 hz. a flexible hybrid class-d output stage offers four modes of operation: standard class-d (sd) mode of- fers full audio bandwidth and high audio performance; hybrid class-d (hd) mode o ffers a substantial reduc- tion in idle power consumption with an integrated class- h controller; reduced frequency class-d (fsd) mode reduces the output switching frequency, producing low- er electromagnetic interference (emi); and reduced frequency hybrid class-d (fhd) mode produces both the lower idle power consum ption of hd mode and the reduced emi benefits of fsd mode. requiring minimal external components and pcb space, the cs35l01 and cs35l03 are available in a 1.2 mm x 1.2 mm, 9-ball wlcsp package in commer- cial grade (-10c to +70c). please see ?ordering information? on page 33 for package options and gain configurations. cs35l01/03 apr '10 ds909a2
cs35l01/03 2 ds909a2 table of contents 1. ball descriptions for cs35l01 & cs35l03 .. ............................................................................ 5 2. digital ball configurations ................................................................................................ ..... 6 3. typical connection diagrams ................................................................................................ ... 7 4. characteristics & specifications ............... ................. ................ ................ ................ ........... 8 recommended operating conditions .................................................................................... 8 absolute maximum rating s ............... ................. ................ ................ ............. ............. ............ .. 8 electrical characteristics - all operational modes ................................................... 9 electrical characteristics - sd mode ................................................................................ 10 electrical characteristics - fsd mode .............................................................................. 11 electrical characteristics - hd mode ................................................................................ 12 electrical characteristics - fhd mode ............................................................................. 13 digital interface specifications and characteristics ............................................... 14 power-up & power-down characteristics ........................................................................ 14 5. applications ............................................................................................................... .................... 15 5.1 mode descriptions ......................................................................................................... .............. 15 5.1.1 standard class-d modes of operation ................................................................................. 15 5.1.1.1 sd mode ............................................................................................................... ..... 15 5.1.1.2 fsd mode .............................................................................................................. .... 15 5.1.2 hybrid class-d modes of operation ............ .......................................................................... 1 5 5.1.2.1 hd mode ............................................................................................................... ..... 16 5.1.2.2 fhd mode .............................................................................................................. ... 16 5.2 reducing the gain with external series resistors ........................................................................ 16 5.3 output filtering with the cs35l01/03 ...................................................................................... ...... 17 5.3.1 reduced filter order with the cs35l01/03 .......................................................................... 17 5.3.2 filter component selection .............................................................................................. ..... 17 5.3.3 output filter power dissipation consideratio ns .................................................................... 18 5.3.3.1 conduction losses for all modes of oper ation ......................................................... 18 5.3.3.2 switching losses in sd/f sd mode ........................................................................... 18 5.3.3.3 switching losses in hd/fhd. .................................................................................... 18 5.4 power-up and power-down ................................................................................................... ....... 19 5.4.1 recommended power-up sequence .................................................................................... 19 5.4.1.1 zero-crossing on power-up functionality ................................................................. 19 5.4.2 recommended power-down sequence ............................................................................... 20 5.5 over temperature protection ............................................................................................... ......... 20 6. typical performance plots .................................................................................................. ... 21 6.1 sd mode typical performance plots ............. ............................................................................ .... 21 6.2 fsd mode typical performance plots ........................................................................................ ... 23 6.3 hd mode typical performance plots ......................................................................................... .... 25 6.4 fhd mode typical performance plots ........... ............................................................................. ... 27 7. parameter definitions ...................................................................................................... .......... 29 8. packaging and thermal information .................................................................................. 30 8.1 package drawings and dimensions ........................................................................................... ... 30 8.2 recommend pcb footprint and routing configur ation ................................................................ 31 8.3 package thermal performance ............................................................................................... ...... 31 8.3.1 determining maximum ambien t temperature ....................................................................... 32 9. ordering information ....................................................................................................... ......... 33 10. revision history .......................................................................................................... ................ 33
cs35l01/03 ds909a2 3 list of figures figure 1. top view of wlcsp pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 2. typical connection diagram for sd & fsd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. typical connection diagram for hd & fhd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 4. adjusting gain via external seri es resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. optional output filter components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. power-up timing with input zero -crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 7. power up timing without input zero-crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 8. thd+n vs. output power - sd mode r l =8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 9. thd+n vs. output power - sd mode r l =4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 10. thd+n vs. frequency - sd mode vbatt = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 11. thd+n vs. frequency - sd mode vbatt = 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 12. thd+n vs. frequency - sd mode vbatt = 3.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 13. frequency response - sd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 figure 14. idle current draw vs. vbatt - sd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 15. output power vs. vbatt - sd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 16. efficiency vs. output power - sd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 17. efficiency vs. output power - sd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 18. supply current vs. output power - sd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 19. supply current vs. output power - sd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 20. thd+n vs. output power - fsd mode r l =8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 21. thd+n vs. output power - fsd mode r l =4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 22. thd+n vs. frequency - fsd mode vbatt = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 23. thd+n vs. frequency - fsd mode vbatt = 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 24. thd+n vs. frequency - fsd mode vbatt = 3.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 25. frequency response - fsd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 26. idle current draw vs. vbatt - fsd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 27. output power vs. vbatt - fsd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 28. efficiency vs. output power - fsd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 29. efficiency vs. output power - fsd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 30. supply current vs. output power - fsd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 31. supply current vs. output power - fsd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 32. thd+n vs. output power - hd mode r l =8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 33. thd+n vs. output power - hd mode r l =4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 34. thd+n vs. frequency - hd mode vbatt = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 35. thd+n vs. frequency - hd mode vbatt = 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 36. thd+n vs. frequency - hd mode vbatt = 3.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 37. frequency response- hd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 38. idle current draw vs. vbatt - hd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 39. output power vs. vbatt - hd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 40. efficiency vs. output power - hd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 41. efficiency vs. output power - hd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 42. supply current vs. output power - hd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 43. supply current vs. output power - hd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 44. thd+n vs. output power - fhd mode r l =8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 45. thd+n vs. output power - fhd mode r l =4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 46. thd+n vs. frequency - fhd mode vbat t = 5.0 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 47. thd+n vs. frequency - fhd mode vbat t = 4.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 48. thd+n vs. frequency - fhd mode vbat t = 3.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 49. frequency response - fhd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 50. idle current draw vs. vbatt - fhd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 51. output power vs. vbatt - fhd mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 52. efficiency vs. output power - fhd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
cs35l01/03 4 ds909a2 figure 53. efficiency vs. output power - fhd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 54. supply current vs. output power - fhd mode r l =8 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 55. supply current vs. output power - fhd mode r l =4 +33 h . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 list of tables table 1. lfilt+ and mode operation configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 2. ja specification for typical pcb designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
cs35l01/03 ds909a2 5 1. ball descriptions for cs35l01 & cs35l03 ball name # description in+ a1 positive analog input ( input ) - differential positive audio signal input. mode a2 switching mode ( input ) - controls the output switching modes of the cs35l01/03. out- a3 negative pwm output ( output ) - differential negative pwm output. lfilt+ b1 low drop out regulator filter ( output ) - bypass capacitor connection point for internal ldo. con- necting this net to vbatt places the device into sd mode. vbatt b2 positive analog power supply ( input ) - positive power supply input. gnd b3 ground ( input ) - power supply ground. in- c1 negative analog input ( input ) - differential negative audio signal input. sd c2 shutdown ( input ) - pulling this net low places the cs35l01/03 in shutdown. out+ c3 positive pwm output ( output ) - differential positive pwm output. a1 in+ a2 mode a3 out- b1 lfilt + b2 vbatt b3 gnd c1 in- c2 sd c3 out+ figure 1. top view of wlcsp pinout (looking down through die)
cs35l01/03 6 ds909a2 2. digital ball configurations see (note 1) and (note 2) below the table. note: 1. refer to specification table ?digital interface specifications and characteristics? on page 14 for details on the digital i/o characteristics. 2. i/o voltage levels must not exceed the voltage listed in table ?absolute maximum ratings? on page 8 . power supply i/o name ball direction internal connections configuration vbatt sd c2 input no internal pull up hysteresis on cmos input mode a2 input no internal pull up hysteresis on cmos input
cs35l01/03 ds909a2 7 3. typical connec tion diagrams figure 2. typical connecti on diagram for sd & fsd mode figure 3. typical connectio n diagram for hd & fhd mode note: 3. the value of the capacitance connected to the lfilt+ net should not exceed 4.7 f. presence of a capacitance above 4.7 f will prevent proper hd and fhd operation. audio in+ audio in- system controller gnd ain+ ain+ mode out+ out- 2.5v - 5v vbatt lfilt+ 10 uf 0. 1uf sd 1uf 0.1 uf 2.5v - 5v 10 uf audio in+ audio in- system controller gnd ain+ ain+ mode out+ out- vbatt lfilt+ sd (note 3)
cs35l01/03 8 ds909a2 4. characteristics & specifications test conditions (unless otherwise specified): gnd = 0 v; all voltages with respect to ground; input signal = 997 hz differential sine; t a = 25c; vbatt = 5 v; r l =8 ; 10 hz to 20 khz measurement bandwidth; measurements tak- en with aes17 measurement f ilter and audio precision aux-0025 passive filter. recommended operating conditions gnd = 0 v; all voltages with respect to ground. please see (note 4) . absolute maximum ratings gnd = 0 v; all voltages with respect to ground. warning: operation at or beyond these limits may result in permanent damage to the device. notes: 4. functionality is not guaranteed or implied outside of these limits. operation outside of these limits may adversely affect device reliability. 5. no external loads should be connected to the lfilt+ net. any connection of a load to this point may result in errant operation or perf ormance degradation in the device. parameters symbol min typ max units dc power supply supply voltage vbatt 2.5 5.0 5.5 v temperature ambient temperature t a -10 - +70 c junction temperature t j -10 - +150 c parameters symb ol min max units dc power supply supply voltage vbatt -0.3 6.0 v lfilt+ current (note 5) i vdreg 10 a inputs input current i in -10ma temperature ambient operating temper ature (power applied) t a -20 +125 c storage temperature t stg -65 +150 c
cs35l01/03 ds909a2 9 electrical characteristics - all operational modes note: 6. no external loads should be connected to the lfilt+ net. any connection of a load to this point may result in errant operation or performance degradation in the device. 7. when vbatt is below this threshold (vb lim ), operation is automatica lly restricted to sd mode. 8. when operating in hd or fhd mode and the differential input voltage remains below the input level threshold (v in-ldo ) for a period of time (t ldo ), the pwm outputs will be po wered by the internally generated ldo supply (vldo). 9. when operating in hd or fhd mode and the differential input voltage is above this input level threshold (v in-vbatt ), the pwm outputs will powered di rectly from the vbatt supply. 10. refer to section 5.5 for more informat ion on thermal error functionality. parameters symbol test conditions min typ max units max. current from lfilt+ (note 6) i lfilt+ -10 - a lfilt+ output impedance z lfilt+ -0.7 - vbatt limit for hd/fhd mode (note 7) vb lim -3.0 -vdc input level for entering ldo operation in hd/fhd modes (note 8) v in-ldo cs35l03 cs35l01 - - 0.014?vbatt 0.027?vbatt - - vrms vrms input level for entering vbatt operation in hd/fhd modes (note 9) v in-vbatt cs35l03 cs35l01 - - 0.09 0.18 - - vrms vrms ldo entry time delay t ldo - 800 - ms ldo level for hd/fhd modes vldo - 1.0 - v output offset voltage v offset inputs ac coupled to gnd -+/-2 -mv amplifier gain a v cs35l03 cs35l01 - - 12 6 - - db db shutdown supply current i a(sd) sd = low -0.05 - a mosfet on resistance r ds(on) i bias = 0.5 a - 270 - m thermal error threshold (note 10) t te - 150 - c thermal error retry time (note 10) r te - 100 - ms under voltage lockout threshold uvlo - 1.9 - v total group delay gd - 10 - s operating efficiency output levels at 10% thd+n 8 + 33 h load vbatt = 5 vdc - 90 - % vbatt = 3.7 vdc - 89 - % 4 + 33 h load vbatt = 5 vdc - 84 - % vbatt = 3.7 vdc - 82 - %
cs35l01/03 10 ds909a2 electrical characte ristics - sd mode parameters symbol test conditions min typ max units output power (continuous average) p o thd+n = 1% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.36/0.95/0.73 2.29/1.59/1.21 - - w w thd+n = 10% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.69/1.18/0.91 2.86/1.99/1.52 - - w w total harmonic distortion + noise thd+n p o = 1.0 w -0.02 -% power supply rejection ratio psrr v ripple = 200 mv pp , ainx ac coupled to gnd @ 217 hz @ 1 khz - - 75 75 - - db db common-mode rejection ratio cmrr v ripple =1v pp , f ripple = 217 hz -55 -db signal to noise ratio a-weighted snr a inputs ac coupled to ground, referenced to 1% thd+n (note 12) cs35l03 cs35l01 - - 96 97 - - db db idle channel noise a-weighted icn a ain+ connected to ain- cs35l03 cs35l01 - - 54 49 - - vrms vrms idle channel noise icn ain+ connected to ain- cs35l03 cs35l01 - - 100 100 - - vrms vrms frequency response fr 20 hz to 20 khz -0.1 0 0.4 db output switching frequency f sw1 -192 -khz idle current draw (note 11) i idle ain+ connected ain-, no output load vbatt = 5 vdc vbatt = 4.2 vdc vbatt = 3.7 vdc - - - 1.06 1.00 0.97 - - - ma ma ma input impedance, single ended z in cs35l03 cs35l01 - - 65 100 - - k k input voltage @ 1 % thd+n v iclip r l = 8 (vbatt = 5.0/4.2/3.7 vdc) cs35l03 cs35l01 - - 0.84/0.71/0.62 1.69/1.41/1.23 - - vrms vrms
cs35l01/03 ds909a2 11 electrical characte ristics - fsd mode note: 11. idle current draw (i idle ) is specified without any ou tput filtering. refer to section 5.3 on page 17 for information on ou tput filtering. parameters symbol test conditions min typ max units output power (continuous average) p o thd+n = 1% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.31/0.92/0.71 2.21/1.55/1.17 - - w w thd+n = 10% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.67/1.17/0.91 2.83/1.97/1.51 - - w w total harmonic distortion + noise thd+n p o = 1.0 w - 0.15 - % power supply rejection ratio psrr v ripple = 200 mv pp , ainx ac coupled to gnd @ 217 hz @ 1 khz - - 75 75 - - db db common-mode rejection ratio cmrr v ripple =1v pp , f ripple =217hz -55 -db signal to noise ratio a-weighted snr a inputs ac coupled to ground, referenced to 1% thd+n (note 12) cs35l03 cs35l01 - - 81 81 - - db db idle channel noise a-weighted icn a ain+ connected to ain- cs35l03 cs35l01 - - 300 300 - - vrms vrms idle channel noise icn ain+ connected to ain- cs35l03 cs35l01 - - 660 660 - - vrms vrms frequency response fr 20 hz to 20 khz -4.0 0 0.5 db output switching frequency f sw2 - 76 - khz idle current draw (note 11) i idle ain+ connected ain- , no output load vbatt = 5 vdc vbatt = 4.2 vdc vbatt = 3.7 vdc - - - 0.88 0.86 0.85 - - - ma ma ma input impedance, single ended z in cs35l03 cs35l01 - - 160 240 - - k k input voltage @ 1 % thd+n v iclip r l = 8 (vbatt = 5.0/4.2/3.7 vdc) cs35l03 cs35l01 - - 0.82/0.69/0.60 1.63/1.36/1.20 - - vrms vrms
cs35l01/03 12 ds909a2 electrical characte ristics - hd mode parameters symbol test conditions min typ max units output power (continuous average) p o thd+n = 1% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.36/0.95/0.73 2.29/1.59/1.21 - - w w thd+n = 10% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.69/1.18/0.91 2.86/1.99/1.52 - - w w total harmonic distortion + noise thd+n p o = 1.0 w - 0.02 - % power supply rejection ratio psrr v ripple = 200 mv pp , ainx ac coupled to gnd @ 217 hz @ 1 khz - - 75 75 - - db db common-mode rejection ratio cmrr v ripple =1v pp , f ripple = 217 hz -55-db signal to noise ratio a-weighted snr a inputs ac coupled to ground, referenced to 1% thd+n (note 12) cs35l03 cs35l01 - - 97 98 - - db db idle channel noise a-weighted icn a ain+ connected to ain- cs35l03 cs35l01 - - 49 43 - - vrms vrms idle channel noise icn ain+ connected to ain- cs35l03 cs35l01 - - 86 85 - - vrms vrms frequency response fr 20 hz to 20 khz -0.1 0 0.4 db output switching frequency f sw1 - 192 - khz idle current draw (note 13) i idle ain+ connected ain-, no output load vbatt = 5 vdc vbatt = 4.2 vdc vbatt = 3.7 vdc - - - 0.94 0.94 0.94 - - - ma ma ma input impedance, single ended z in cs35l03 cs35l01 - - 65 100 - - k k input voltage @ 1% thd+n v iclip r l = 8 (vbatt = 5.0/4.2/3.7 vdc) cs35l03 cs35l01 - - 0.85/0.71/0.62 1.69/1.41/1.23 - - vrms vrms
cs35l01/03 ds909a2 13 electrical characte ristics - fhd mode note: 12. snr a db is referenced to the output signal amp litude resulting in the specified output power at thd+n <1%. see ?parameter definitions? on page 29 for more information. 13. idle current draw (i idle ) is specified without any ou tput filtering. refer to section 5.3 on page 17 for information on output filter ing. at idle, the output devices will switch at the same rate in hd and fhd mode. fhd only changes the output switching frequency when the inpu t levels are above the ?input level for entering vbatt op eration in hd/fhd modes (v in-vbatt ) given in ?electrical characteristics - all operational modes? on page 9 . parameters symbol test conditions min typ max units output power (continuous average) p o thd+n = 1% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.31/0.92/0.71 2.20/1.55/1.51 - - w w thd+n = 10% r l = 8 (vbatt = 5.0/4.2/3.7 vdc) r l = 4 (vbatt = 5.0/4.2/3.7 vdc) - - 1.67/1.17/0.91 2.83/1.97/1.51 - - w w total harmonic distortion + noise thd+n p o = 1.0 w - 0.15 - % power supply rejection ratio psrr v ripple = 200 mv pp , ainx ac coupled to gnd @ 217 hz @ 1 khz - - 75 75 - - db db common-mode rejection ratio cmrr v ripple =1v pp , f ripple = 217 hz -55-db signal to noise ratio a-weighted snr a inputs ac coupled to ground, referenced to 1% thd+n (note 12) cs35l03 cs35l01 - - 93 94 - - db db idle channel noise a-weighted icn a ain+ connected to ain- cs35l03 cs35l01 - - 71 66 - - vrms vrms idle channel noise icn ain+ connected to ain- cs35l03 cs35l01 - - 125 125 - - vrms vrms frequency response fr 20 hz to 20 khz -4.0 0 0.5 db output switching frequency f sw1 ldo operation - 192 - khz output switching frequency f sw2 vbatt operation - 76 - khz idle current draw (note 13) i idle ain+ connected ain-, no output load vbatt = 5 vdc vbatt = 4.2 vdc vbatt = 3.7 vdc - - - 0.94 0.94 0.94 - - - ma ma ma input impedance, single ended z in cs35l03 cs35l01 - - 160 240 - - k k input voltage @ 1 % thd+n v iclip r l = 8 (vbatt = 5.0/4.2/3.7 vdc) cs35l03 cs35l01 - - 0.83/0.70/0.61 1.66/1.39/1.22 - - vrms vrms
cs35l01/03 14 ds909a2 digital interface specific ations and characteristics power-up & power-do wn characteristics note: 14. start-up time (t start ) refers to the internal start-up time from when sd is released to when the device is ready to activate th e pwm outputs. the total power-up time from sd release to the pwm outputs becoming active will vary based on the input signal, not exceeding the start-up time + zero crossing power-up timeout (t start +t timeout ). for more information, refer to section 5.4 . parameters symb ol min max units input leakage current i in -10 a input capacitance -10pf sd pulse width requirement 1 - ms logic i/os (applicable to gain_sel, mode, and sd ) high-level input voltage v ih 0.7?vbatt - v low-level input voltage v il - 0.3?vbatt v parameters symbol test c onditions min typ max units start-up time (note 14) t start after low-to-high sd pin transition edge -18-ms zero crossing power-up timeout t timeout no audio input applied -25-ms power-down time t off after high-to-low sd pin transition edge -1-ms
cs35l01/03 ds909a2 15 5. applications 5.1 mode descriptions the cs35l01/03 devices can be operated in one of four operating modes, determined by the mode pin and the lfilt+ pin. the four modes of operation ar e standard class-d operation (sd), reduced frequency standard class-d operation (fsd), hybrid class-d operation (hd), and reduced frequency hybrid class- d operation (fhd). each of these modes can be leveraged to optimize different performance criteria in an array of applications. table 1. lfilt+ and mode operation configurations 5.1.1 standard class-d modes of operation 5.1.1.1 sd mode standard class-d (sd) mode supports full audio bandwidth with very good snr and thd+n perfor- mance. this mode of operation is charac terized by a traditional closed loop, analog ? modulated class- d amplifier. with an output switch ing frequency of 192 khz, this mode ensures flat frequency response across the entire audio frequency range. 5.1.1.2 fsd mode the reduced frequency class-d (fsd) mode provides competitive audio performance and a reduction in radiated emissions by decreasing the switching freq uency of the output devices to 76 khz. this reduc- tion in switching frequency reduces the high-frequency energy being created by the output switching events. idle channel noise is slight ly higher in this mode of operat ion than sd mode, with the trade-off being better emi performance and power consumption. 5.1.2 hybrid class-d modes of operation hybrid class-d and reduced frequenc y hybrid class-d modes of operatio n allows the rail voltage for the output devices to switch between a high voltage ne t and a low voltage net depending on the audio content being amplified. this is ex plained in more detail in section 5.1.2.1 and section 5.1.2.2 . operation in these modes requires that the voltage present on the vba tt pin be above the level listed as ?vbatt limit for hd/fhd mode (vb lim )? in ?electrical characteristics - a ll operational modes? on page 9 . if it is not, hd and fhd modes of operati on of the device will automatically be di sabled and operation will be limited to the sd mode of operation. mode connected to: gnd vbatt lfilt+ connected to: vbatt reduced frequency class-d mode (fsd) standard class-d mode (sd) filter cap to ground reduced frequency hybrid class-d mode (fhd) hybrid class-d mode (hd)
cs35l01/03 16 ds909a2 in both hd and fhd mode, the value of the capacit ance connected to the lfilt+ pin must not exceed 4.7 f. if this value is greater than 4.7 f, it will prevent the rail voltage of the output devi ces from transi- tioning properly between vbatt and the internal ldo. 5.1.2.1 hd mode hybrid class-d mode (hd) provides competitive analog performance with a substantial reduction in idle power dissipation and radiation emissions. in this mode, the output switches at 192 khz and a secondary supply is derived from vbatt using an internal 1.0- vdc low drop-out linear regu lator (ldo). when the output signal is at a low amplitude, the class-d output stage begins to switch from the lower rail voltage created by the internal ldo. this not only decreases idle power cons umption when output capacitors are used, but also reduces electromagnet ic emissions by reducing the amplitude of the square waves being created at the output of the cs35l01/03 when operating at low amplitude or idle power. 5.1.2.2 fhd mode the reduced frequency hybrid class-d (fhd) mode pr ovides the best overall emi performance and the lowest power consumption with slig htly decreased frequency response near the top frequency range of the audio band, for high amplitude signals. in this mode of operation, the output switching frequency is reduced to 76 khz during high amplitude transients on the output. the threshold at which this transition from 192-khz to 76-khz switching ra te occurs is given as the input level threshold for fhd operation in ?electrical characteristics - fhd mode? on page 13 . combined with the lower amplitude switching offered by the hybrid design, this reduction in switching ener gy dramatically reduces th e emissions levels of the output stage and its associated components. 5.2 reducing the gain with external series resistors if necessary, it is possible to decrease the gain of the cs35l01/03 by adding series resistors to the audio input signal as is shown in figure 4 below. if input resistors are added, the new gain of the am plifier can be determined by the following equation: where: a v(adjusted) = the new, adjusted gain of the system audio in+ audio in- r in r in ain+ ain- x x figure 4. adjusting gain via external series resistance a v adjusted () a v 20 ? z in z in z ext + ------------- ------------- ?? ?? log =
cs35l01/03 ds909a2 17 z in = input impedance of the device being used (see ?electrical characteristics - sd mode? on page 10 , ?electrical characteristics - fsd mode? on page 11 , ?electrical characteristics - hd mode? on page 12 , or ?electrical characteristics - fhd mode? on page 13 for this value.) z ext = value of the resistor added in series with the inputs a v = original gain of the device being used (see ?electrical characteristics - all operational modes? on page 9 for this value.) 5.3 output filtering with the cs35l01/03 the cs35l01/03 is specifically designed to minimize radiated electromagnetic interference (emi) signals. all of the devices are capable of me eting all stated data sheet performance numbers with no special filtering required. additionally, the device has shown to be bel ow the compliance limits of both fcc and cispr test- ing with no external filtering required. ultimately, compliance with any radiated emissions requ irements depends significantly on the entire system under test. in applications were system-level trade-of fs such as compromised component layout or lengthy speaker wires have increased emissions levels, a passiv e output filter can be ad ded to the outputs of the device in order to decrease emi levels. 5.3.1 reduced filter order with the cs35l01/03 in applications which require an output filter, the uni que design of the cs35l01/03 allows a much smaller, less expensive output filter to be used than what is normally found in class-d amp lifiers. in contrast to a second order filter implemented with a series inductive element (traditional inductor or ferrite beads) and a shunt capacitive element, basic filtering for the cs35l01/03 is accomplished by a single-order capaci- tive element attached to the outx terminals. this is highlighted in figure 5 below. of course, if the system requires more aggressive filtering, a ferrite bead can be added in series with the outputs to further atten- uate system level noise. 5.3.2 filter component selection usually, the need for output filtering is determined after the system under test has failed emi testing. dur- ing this testing, problem frequencies are easily identified by the peaks which appear in the spectral plots gathered in the emi testing. selection of the filter components should ensure that shunt elements (i.e. c filt in figure 5 ) present a very low impedance at the frequency corresponding to the tallest peak in the spectral plot. if needed, series components such as ferrite beads (i.e. l filt in figure 5 ) should be chosen to present a very high imped- ance at the frequency corresponding to the tallest peak in the spectral plot. careful attention should be paid to t he current-carrying capabilities of any included ferr ite beads and the impedance of the ferrite beads in the audio band. a proper trade-off in ferrite bead selection is one that c filt c filt traditional 2 nd order optional filter cs35l01/03?s minimized optional filter out+ out- c filt c filt x x l filt l filt out+ out- x x figure 5. optional output filter components
cs35l01/03 18 ds909a2 allows the ferrite bead to sufficiently attenuate t he problematic high-frequency emissions without compro- mising audio performance. 5.3.3 output filter power dissipation considerations in systems without inductiv e series elements like inductors or ferrite beads, power losses in the output filter are equal to the switching losses that occur in the system due to the cyclic al charging and discharging of capacitors connected to the amplifier outputs. in systems that require an inductive series element, con- ducted losses also occurs due to the series impedance added to the output path. 5.3.3.1 conduction losses for all modes of operation for all modes of operation (sd, fs d, hd, and fhd) of the cs35l01/03, the conduction losses are gov- erned by the equation: where: p = power dissipated in the series impedance. i = rms ac output current z = impedance of the series element at the frequency of the ac current this equation neglects any series impedances presente d by the pcb traces or speaker wires in the output path. 5.3.3.2 switching loss es in sd/fsd mode switching losses in sd/fsd mode are governed by the equation where: p = power dissipated in the capacitor (neglecting parasites). c = value of filtering capacitor v = peak voltage developed across the capacitor f = switching frequency of the outputs these calculations are straightforward, as the peak vo ltage is simply the voltage level attached to vbatt, the capacitor is the value of capacitor that has been added for filtering (neglecting parasitic board capac- itances), and the frequency is 192 khz or 76 khz for sd and fsd, respectively. 5.3.3.3 switching losses in hd/fhd. many factors affect the switching losses when the de vice is operated in hd/fhd mode. these factors in- clude the frequency of the content being amplified, the voltage level of vbatt, and the amplitude of the output signal will factor into both the voltage presented across the capacitors and the frequency at which the capacitors are charged or discharged. pi 2 z = p 1 2 -- - cv 2 f =
cs35l01/03 ds909a2 19 static signals (i.e. sine waves at a fixed amplitude) are easier to consid er than are dynamic signals (i.e. musical content), as they are governed by the same equation as that listed in section 5.3.3.1 and section 5.3.3.2 on page 18 . modifications to that equation are limited to the voltage term (v) and the frequency term (f), depending on whether the st atic input signal amplitude is caus ing the output devices to switch at 76 khz or 192 khz, and to operate off of the vbatt supply or off of the internally generated ldo. it is important to note that the hd and fhd modes offer significant improvement over traditional class-d in idle power dissipation w hen an external output filter is necessa ry. this is because the voltage term (v) is significantly reduced in hd and fhd mode. as can be seen in the equation, this is notable because reduction in the operating voltage reduce s power losses not linearly, but instead exponentially - due to the voltage squared term (v 2 ). it is also notable that when opera ted at high output levels, fhd modes also offers unique improvement in output filter losses, due to reducing the switching frequency (f) at higher out- put levels. 5.4 power-up and power-down when pulled to a logic low state, the sd pin tristates the outputs and shuts down the cs35l01/03 device, putting it into a low power mode. 5.4.1 recommended power-up sequence 1. with the sd pin pulled low, apply power to the cs35l01/03 and wait for the power supply to be stable. 2. set the sd pin high to begin normal operation. 5.4.1.1 zero-crossing on power-up functionality the cs35l01/03 implements an input-signal zero-cross ing detection function th at is enabled during pow- er-up. this function is designed to prevent audible ar tifacts and eliminate any need to mute the amplifier?s input audio signal during the power-up process. after a minimum start-up time of t start , the cs35l01/03 will b egin to detect input- signal zero-crossings. the amplifier will then en able its switching outputs at the time of the first detected input-signal zero-cross- ing transition. if no input-signal zero-crossing is detected before t timeout , the zero-crossing function will tim- eout and the outputs will be gin switching immediately. both t start and t timeout are specified in ?power-up & power-down characteristics? on page 14 . out+/- shut-down / low power mode t start sd v ih device ready: waiting for zero crossing input signal or t timeout internal start-up v il pwm out+/- active vbatt or vldo in+/- t timeout figure 6. power-up timing with input zero-crossing figure 7. power up timing without input zero-crossing out+/- shut-down / low power mode t start sd v ih device ready: waiting for zero crossing input signal or t timeout internal start-up v il pwm out+/- active vbatt or vldo in+/- t timeout
cs35l01/03 20 ds909a2 5.4.2 recommended power-down sequence 1. mute the audio supplied to the cs35l01/03. 2. pull the sd pin low in order to reset the device and put it into the low power mode. 3. the power supply to the cs35l01/03 can now be removed. 5.5 over temperature protection the cs35l01/03 is internally protect ed against thermal overload. built in die temperature sensing circuitry monitors the die temperatur e and will place the device into shut-dow n if thermal overload occurs. a ther- mal overload is characterized by the die temper ature reaching the thermal error threshold (t te ) at which time the outputs will tris tate and shut down. if the device has entered into shut-down due to a thermal overload, the die temperature must remain be- low the thermal error threshold (t te ) for the time specified by the thermal error retry time (r te ) in order for the device to automatically return to normal operation. both t te and r te are specified in ?electrical characteristics - a ll operational modes? on page 9 .
cs35l01/03 ds909a2 21 6. typical performance plots test conditions (unless other wise specified): gnd = 0 v; all voltages with respect to ground; a v = 6 db; input signal = 997 hz differential sine; t a = 25c; vbatt = 5.0 v; r l =8 ; 10 hz to 20 khz measurement ba ndwidth; measurements taken with aes17 measurement filter and audio precision aux-0025 passive filter. 6.1 sd mode typical performance plots 0.007 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 2 2m 5m 10m 20m 50m 100m 200m 500m 1 w 0.007 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 3 2m 5m 10m 20m 50m 100m 200m 500m 1 2 w figure 8. thd+n vs. output power - sd mode r l =8 figure 9. thd+n vs. output power - sd mode r l =4 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 11. thd+n vs. frequency - sd mode vbatt = 4.2 v 1.0 w 0.5 w 0.75 w 0.5 w 0.1 w 0.1 w figure 10. thd+n vs. frequency - sd mode vbatt = 5.0 v -4 +4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 +3 +3.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 12. thd+n vs. frequency - sd mode vbatt = 3.7 v figure 13. frequency response - sd mode 0.625 w 0.1 w 0.5 w 4 8
cs35l01/03 22 ds909a2 note: 15. ?idle current draw vs. vbatt - sd mode? capacitor values refer to c filt when configured as the ?cs35l01/03?s minimized optional output filter,? shown in figure 5 on page 17 . 0.00 1.00 2.00 3.00 4.00 5.00 6.00 7.00 2.5 3 3.5 4 4.5 5 5.5 vbatt (v) idle current draw (ma) figure 14. idle current draw vs. vbatt - sd mode r l =8 +33 h (note 15) figure 15. output power vs. vbatt - sd mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vbatt supply voltage (v) output power (w) r l = 8 1% thd+n ratio r l = 8 10% thd+n ratio r l = 4 1% thd+n ratio r l = 4 10% thd+n ratio no filter 470 pf 1000 pf 2200 pf 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 output power (w) efficiency (%) 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) efficiency (%) figure 16. efficiency vs . output power - sd mode r l =8 +33 h figure 17. efficiency vs. output power - sd mode r l =4 +33 h 4.2 v 3.7 v 4.2 v 3.7 v 5.0 v 5.0 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) supply current (a) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0 0.5 1 1.5 2 2.5 3 output power (w) current consumption (a) figure 18. supply current vs. output power - sd mode r l =8 +33 h figure 19. supply current vs. output power - sd mode r l =4 +33 h 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v
cs35l01/03 ds909a2 23 6.2 fsd mode typical performance plots 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 2 2m 5m 10m 20m 50m 100m 200m 500m 1 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 3 2m 5m 10m 20m 50m 100m 200m 500m 1 2 w figure 20. thd+n vs. ou tput power - fsd mode r l =8 figure 21. thd+n vs. output power - fsd mode r l =4 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 22. thd+n vs. frequency - fsd mode vbatt = 5.0 v figure 23. thd+n vs. frequency - fsd mode vbatt = 4.2 v 1.0 w 0.5 w 0.75 w 0.5 w 0.1 w 0.1 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz -4 +4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 +3 +3.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 24. thd+n vs. frequency - fsd mode vbatt = 3.7 v figure 25. frequency response - fsd mode 0.625 w 0.1 w 0.5 w 4 8
cs35l01/03 24 ds909a2 note: 16. ?idle current draw vs. vbatt - fsd mode? capacitor va lues refer to c filt when configured as the ?cs35l01/03?s minimized optional output filter?, shown in figure 5 on page 17 . 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 2.5 3 3.5 4 4.5 5 5.5 vbatt (v) idle current draw (ma) figure 26. idle current draw vs. vbatt - fsd mode r l =8 +33 h (note 16) figure 27. output power vs. vbatt - fsd mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vbatt supply voltage (v) output power (w) r l = 8 1% thd+n ratio r l = 8 10% thd+n ratio r l = 4 1% thd+n ratio r l = 4 10% thd+n ratio 470 pf no filter 1000 pf 2200 pf 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) efficiency (%) 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 output power (w) efficiency (%) figure 28. efficiency vs. output power - fsd mode r l =8 +33 h figure 29. efficiency vs. output power - fsd mode r l =4 +33 h 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v 5.0 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) supply current (a) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0 0.5 1 1.5 2 2.5 3 output power (w) current consumption (a) figure 30. supply current vs. output power - fsd mode r l =8 +33 h figure 31. supply current vs. output power - fsd mode r l =4 +33 h 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v
cs35l01/03 ds909a2 25 6.3 hd mode typical performance plots 0.007 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 2 2m 5m 10m 20m 50m 100m 200m 500m 1 w 0.007 10 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 3 2m 5m 10m 20m 50m 100m 200m 500m 1 2 w figure 32. thd+n vs. output power - hd mode r l =8 figure 33. thd+n vs. output power - hd mode r l =4 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 34. thd+n vs. frequency - hd mode vbatt = 5.0 v figure 35. thd+n vs. frequency - hd mode vbatt = 4.2 v 1.0 w 0.5 w 0.75 w 0.5 w 0.1 w 0.1 w 0.001 10 0.002 0.005 0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz -4 +4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 +3 +3.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 36. thd+n vs. frequency - hd mode vbatt = 3.7 v figure 37. frequency response- hd mode 0.625 w 0.1 w 0.5 w 4 8
cs35l01/03 26 ds909a2 note: 17. ?idle current draw vs. vbatt - hd mode? capacitor values refer to c filt when configured as the ?cs35l01/03?s minimized optional output filter?, shown in figure 5 on page 17 . when vbatt is below ?vbatt limit for hd/fhd mode? (vb lim ), operation is restricted to sd mode. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 2.5 3 3.5 4 4.5 5 5.5 vbatt (v) idle current draw (ma) figure 38. idle current draw vs. vbatt - hd mode r l =8 +33 h (note 17) figure 39. output power vs. vbatt - hd mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vbatt supply voltage (v) output power (w) r l = 8 1% thd+n ratio r l = 8 10% thd+n ratio r l = 4 1% thd+n ratio r l = 4 10% thd+n ratio 470 pf no filter 1000 pf 2200 pf 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) efficiency (%) 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 output power (w) efficiency (%) figure 40. efficiency vs. output power - hd mode r l =8 +33 h figure 41. efficiency vs. output power - hd mode r l =4 +33 h 4.2 v 3.7 v 4.2 v 3.7 v 5.0 v 5.0 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) supply current (a) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0 0.5 1 1.5 2 2.5 3 output power (w) current consumption (a) figure 42. supply current vs. output power - hd mode r l =8 +33 h figure 43. supply current vs. output power - hd mode r l =4 +33 h 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v
cs35l01/03 ds909a2 27 6.4 fhd mode typical performance plots 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 2 2m 5m 10m 20m 50m 100m 200m 500m 1 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 1m 3 2m 5m 10m 20m 50m 100m 200m 500m 1 2 w figure 44. thd+n vs. output power - fhd mode r l =8 figure 45. thd+n vs. output power - fhd mode r l =4 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 46. thd+n vs. frequency - fhd mode vbatt = 5.0 v figure 47. thd+n vs. frequency - fhd mode vbatt = 4.2 v 1.0 w 0.5 w 0.75 w 0.5 w 0.1 w 0.1 w 0.01 10 0.02 0.05 0.1 0.2 0.5 1 2 5 % 20 20k 50 100 200 500 1k 2k 5k 10k hz -4 +4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 +0 +0.5 +1 +1.5 +2 +2.5 +3 +3.5 d b r a 20 20k 50 100 200 500 1k 2k 5k 10k hz figure 48. thd+n vs. frequency - fhd mode vbatt = 3.7 v figure 49. frequency response - fhd mode 0.625 w 0.1 w 0.5 w 4 8
cs35l01/03 28 ds909a2 note: 18. ?idle current draw vs. vbatt - fhd mode? capacitor values refer to c filt when configured as the ?cs35l01/03?s minimized optional output filtering? shown in figure 5 on page 17 . when vbatt is below ?vbatt limit for hd/fhd mode? (vb lim ), operation is restricted to sd mode. 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 2.5 3 3.5 4 4.5 5 5.5 vbatt (v) idle current draw (ma) figure 50. idle current draw vs. vbatt - fhd mode r l =8 +33 h (note 18) figure 51. output power vs. vbatt - fhd mode 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 2.5 3.0 3.5 4.0 4.5 5.0 5.5 vbatt supply voltage (v) output power (w) r l = 8 1% thd+n ratio r l = 8 10% thd+n ratio r l = 4 1% thd+n ratio r l = 4 10% thd+n ratio 470 pf no filter 1000 pf 2200 pf 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) efficiency (%) 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0 0.5 1 1.5 2 2.5 3 output power (w) efficiency (%) figure 52. efficiency vs. output power - fhd mode r l =8 +33 h figure 53. efficiency vs . output power - fhd mode r l =4 +33 h 4.2 v 3.7 v 4.2 v 3.7 v 5.0 v 5.0 v 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 0.25 0.5 0.75 1 1.25 1.5 1.75 output power (w) supply current (a) 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 0 0.5 1 1.5 2 2.5 3 output power (w) current consumption (a) figure 54. supply current vs. output power - fhd mode r l =8 +33 h figure 55. supply current vs. output power - fhd mode r l =4 +33 h 5.0 v 4.2 v 3.7 v 5.0 v 4.2 v 3.7 v
cs35l01/03 ds909a2 29 7. parameter definitions signal to noise ratio (snr) the ratio of the rms value of the output signal, where p out is equivalent to the specified output power at thd+n<1%, to the rms value of the noise floor with no input signal applied and measured over the spec- ified bandwidth, typically 20 hz to 20 khz. this meas urement technique has been accepted by the electron- ic industries association of japan, eiaj cp-307. expressed in decibels. total harmonic distorti on + noise (thd+n) the ratio of the rms value of the signal to the rms su m of all other spectral components over the specified band width (typically 10 hz to 20 kh z), including distortion components. expressed in decibels. measured at -1 and -20 dbfs as suggested in aes17-1991 annex a. idle channel noise (icn) measure of the signal present on the outputs of the device when no audio signal is presented to the input pins. for this test, both input pins are shorted together, setting the diff erential signal to them to zero.
cs35l01/03 30 ds909a2 8. packaging and thermal information 8.1 package drawings and dimensions (note 19) note: 19. dimensioning and tolerance per asme y 14.5m-1994. inches millimeters note dim min nom max min nom max x 0.047 0.048 0.049 1.195 1.215 1.235 19 y 0.047 0.048 0.049 1.195 1.215 1.235 19 b 0.009 0.011 0.012 0.240 0.270 0.300 e - 0.015 - - 0.400 bsc - 19 a 0.018 0.020 0.022 0.475 0.515 0.555 19 a1 0.006 0.007 0.008 0.175 0.190 0.205 19 a2 0.012 0.013 0.014 0.300 0.325 0.350 19 jedec #: mo-220 controlling dimension is millimeters. a2 y x b e e a1 a 9 solder spheres 9 ball wlcsp
cs35l01/03 ds909a2 31 8.2 recommend pcb footprint an d routing configuration to ensure high-yield manufacturabilit y, the pcb footprint for the cs35l0 1/03 should be constructed with strict adherence to the specifications given in ipc-610. departure from this specification significantly in- creases the probability of solder bri dging and other manu facturing defects. routing of the traces into and out of the cs35l01/03 device should also be given consideration to avoid manufacturing issues. 8.3 package thermal performance class-d amplifiers, though highly efficient, will produce some amount of heat through the process of ampli- fying the audio signal. as is well unde rstood, this amount of heat is very small compared to traditional class ab amplifiers. even so, as power levels increase an d package sizes de crease, careful consideration must be given to ensure thermal energy is removed from the devi ce as efficiently as possib le so that its operating temperature is kept under its over-temperature error threshold. the thermal impedance, ja is a measurement of the impedance to the flow of thermal energy out of the device to the environment surrounding the device. this specification is di rectly related to the ability of the pcb to which the cs35l01/03 is attached to transfer the heat from the device. the thermal impedance from the junction of the device to the ambient surrounding the device and the thermal impedance from the device into the pcb is shown in table 2 . . table 2. ja specification for typical pcb designs note: 20. test printed circuit board as sembly (pcba) constructed in accordance with jedec standard jesd51-9. two signal, two plane (2s2p) pcb utilized. 21. test conducted with still air in accordance with jedec standards j esd51, jesd51-2a, and jesd51-8. parameter (note 20) , (note 21) symbol min typical max units junction to ambient thermal impedance a -92-c/watt junction to printed circuit board thermal impedance pcb -67-c/watt
cs35l01/03 32 ds909a2 8.3.1 determining maximu m ambient temperature to determine (to a first order approximation) the maximum ambient temperature in which the cs35l01/03 will operate, the following equations can be used: where: t max = the maximum ambient temperature in which the device can operate. t op = the operating temperature of the device, given a dissipated power ? p max? and a known thermal impedance ? ja ?. t te = the over-temperature error threshold, given in the ?electrical characterist ics - all operational modes? section on page 9 . ja = the thermal impedance of the device and pcb. (t his value is highly subjective to a number of ap- plication specific scenarios. the numbers given in table 2 on page 31 can be used for a first order ap- proximation, but proper characterization of the app lication?s specific pcb an d supporting mechanicals is needed to increase the accuracy of the result achieved here.) p max = the maximum power at which th e amplifier will be operated contin uously. (for conservative esti- mates, the 10% thd+n rated power given in ?electrical characteristics - sd mode? section on page 10 , ?electrical characteristics - fsd mode? section on page 11 , ?electrical characteristics - hd mode? section on page 12 , or ?electrical characteristics - fhd mode? section on page 13 can be used. however, this method will predict higher operating temperatures than what may be seen in the application, since power content of audio signals is much smaller than that of the sine wave used to establish the power specifica- tions.) = the efficiency of the device at the power p max . t op ja 1 ? () p max () = t max t te t op ? =
cs35l01/03 ds909a2 33 9. ordering information 10.revision history product description package pb-free grade temp range container order# cs35l01 2.9 w mono audio amplifier with default +6 db gain 9- wlcsp yes commercial -10 to +70c tape and reel CS35L01-CWZR cs35l03 2.9 w mono audio amplifier with default +12 db gain 9- wlcsp yes commercial -10 to +70c tape and reel cs35l03-cwzr release changes a1 ? initial release a2 ? updated all output switching frequency references to f sw1 from 200 khz to 192 khz. ? updated all output switching frequency references to f sw2 from 80 khz to 76 khz. ? updated cs35l0x part number references to cs35l01/03. ? updated front page title, feat ures, and common applications. ? updated front page block diagram. ? updated package dimensions in section 8. packaging and thermal information . ? updated section 3. typical connection diagrams to show 10 f and 0.1 f power-supply decoupling capacitors. ? reorganized location of individual specifications in electrical characteristics tables based on measured device performance in different operational modes ( ?electrical characteristics - all operational modes? on page 9 , ?electrical characteristics - sd mode? on page 10 , ?electrical characteristics - fsd mode? on page 11 , ?electrical characteristics - hd mode? on page 12 , and ?electrical characteristics - fhd mode? on page 13 ). ? the following specification changes have been made in ?electrical characteristics - sd mode? on page 10 , ?electrical characteristics - fsd mode? on page 11 , ?electrical characteristics - hd mode? on page 12 , and ?electrical characteristics - fhd mode? on page 13 : ? added ?common-mode rejection ratio? test conditions (v ripple =1v pp and f ripple = 217 hz) ? updated ?signal to noise ratio? to be specified as a-weighted ? updated ?idle channel noise? to be sp ecified as both a-weighted & unweighted ? updated ?idle current draw? to be specified with no load at 3 voltages (5.0 v, 4.2 v, and 3.7 v) ? changed ?max input before clipping specification to ?input voltage @ 1 % thd+n? ? updated specification typical values for 1% out put power, 10% output power, thd+n @ 1 w, snr a-weighted, idle channel noise a-weighted, idle channel noise (unweighted), frequency response, output switching frequency, inpu t impedance, and input voltage @ 1% thd+n ? updated ?operating efficiency? to be specified with 8 + 33 h and 4 + 33 h in ?electrical characteristics - all oper ational modes? on page 9 . ? modified ?power-up time? specific ation into ?start-up time? and ?zero crossing power-up? and added a cross-reference in ?power-up & power-down characteristics? on page 14 . ? moved power-up and power-down timing specifications from ?electrical characteristics - all operational modes? on page 9 to their own spec ification table, ?power-up & power-down characteristics? on page 14 . ? renamed ?thermal error wait time (w te )? to ?thermal error retry time (r te )? in ?electrical characteristics - all operational modes? on page 9 and in section 5.5 over te mperature protection and added (note 10) thermal error cross reference from spec table to description section. ? updated ?operating efficiency? specification ( ) in ?electrical characteristics - all operational modes? on page 9 . ? updated ?mosfet on resistance? specification (r ds(on) ) in ?electrical characteristics - all operational modes? on page 9 .
cs35l01/03 34 ds909a2 a2 ? updated ?shutdown supply current? specification (i a(sd) ) in ?electrical characteristics - all operational modes? on page 9 . ? added ?mosfet on resistance? test conditions (i bias =0.5a) in ?electrical characteristics - all operational modes? on page 9 . ? section 5.1.1.1 sd mode updated to remove references to edge rate control. ? section 5.1.2.1 hd mode updated to include f sw1 switching frequency and clarify the conditions under which radiated emissions gains occur. ? added section 6. typical performance plots . ? added section 5.4 power-up and power-down . ? modified ?input level threshold for hd/fhd modes? to be split up into ?input level for entering ldo operation in hd/fhd modes? and ?input level for entering vbatt operation in hd/fhd modes? in ?electrical characteristics - all operational modes? on page 9 . ? added ?ldo entry time delay? specification in ?electrical characteristics - all operational modes? on page 9 . ? updated (note 8) and added (note 9) referring to the ?input level thresholds?. ? updated section 5.5 over temperature protection functional description. ? updated out of date specification names, symbols, and cross-references in multiple locations throughout the document. contacting cirrus logic support for all product questions and inquiries, contact a cirrus logic sales representative. to find one nearest you, go to www.cirrus.com . important notice ?advance? product information describes products that are in development and subject to development changes. cirrus logic, inc. and its subsidiaries (?cirrus?) be- lieve that the information contained in this document is accurate and reliable. however, the information is subject to change w ithout notice and is provided ?as is? without warranty of any kind (express or implied). customers are advised to obtain the latest version of relevant information t o verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limit ation of liability. no responsibility is assumed by cirrus fo r the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. this document is the property of cirrus and by furnishing this information, cirrus grants no license, express or implied under any patents, mask work rights, co pyrights, trademarks, trade secrets or other intellectual property rights. cirrus owns the copyrights associated with the information contained herein and gives conse nt for copies to be made of the infor- mation only for use within your organization with respect to cirrus integrated circuits or other products of cirrus. this conse nt does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. certain applications using semi conductor products may involve po tential risks of death, perso nal injury, or severe prop- erty or environmental damage (? critical applications?). cirrus products are not designed, authorized or warranted for use in products surgically implanted into the body, automotive safety or security devices, life su pport products or other crit- ical applications. inclus ion of cirrus products in such appl ications is understood to be full y at the customer?s risk and cir- rus disclaims and makes no warranty, expres s, statutory or implied, including the implied warranties of merchantability and fitness for particular purpose, with regard to any cirrus product that is used in such a manner. if the customer or custom- er?s customer uses or permits the use of cirrus products in cr itical applications, customer agrees, by such use, to fully indemnify cirrus, its officers, directors, employees, distributors and other agents from any a nd all liability, including at- torneys? fees and costs, that may result fr om or arise in connection with these uses. cirrus logic, cirrus, and the cirrus logic logo designs are trademarks of cirrus logic, inc. all other brand and product names in this document may be trademarks or service marks of their respective owners.

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